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Mark J.
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SyoSil is a leader in FPGA/ASIC design and verification solutions, including device firmware and tool development. We advice our clients on how to improve their design and verification methodologies, and deliver turn-key verification flows and Verification IP, based on industry standards such as SystemVerilog/UVM. Our clients include top European and U.S. semiconductor companies, all being respective leaders in their respective product segments (consumer, communication, automotive and surveillance). We are a young and dynamic team of 50+ full time engineers working in an international environment, with very skilled and open-minded colleagues
Asic/fpga design & verification,eda tools,systemverilog,uvm,formal property checking,firmware,and software solutions
Syosil operates in the Semiconductors industry.
Syosil's revenue is 11m - 100m
Syosil has 11 - 50 employees.
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